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| 74ACT74 DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR s s s s s s s s s HIGH SPEED: fMAX = 250 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX) 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY B M (Plastic Package) (Micro Package) ORDER CODES : 74ACT74B 74ACT74M the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. DESCRIPTION The ACT74 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of PIN CONNECTION AND IEC LOGIC SYMBOLS April 1997 1/11 74ACT74 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 13 2, 12 3, 11 SYMBOL 1CLR, 2CLR 1D, 2D 1CK, 2CK NAME AND F UNCTIO N Asyncronous Reset Direct Input Data Inputs Clock Input (LOW-to-HIGH, EdgeTriggered) Asyncronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage 4, 10 5, 9 6, 8 7 14 1PR, 2PR 1Q, 2Q 1Q, 2Q GND VCC TRUTH TABLE INPUTS CLR L H L H H H X: Don't Care OUT PUT S D X X X L H X CK X X X Q L H H L H Qn Q H L H H L Qn F UNCT IO N CLEAR PRESET PR H L L H H H NO CHANGE LOGIC DIAGRAMS This logic diagram has not be used to estimate propagation delays 2/11 74ACT74 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 50 200 -65 to +150 300 Unit V V V mA mA mA mA o o ICC or IGND DC VCC or Ground Current C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature: Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) Parameter Valu e 4.5 to 5.5 0 to VCC 0 to VCC -40 to +85 8 Unit V V V o C ns/V 1) VIN from 0.8 V to 2.0 V 3/11 74ACT74 DC SPECIFICATIONS Symbol Parameter V CC (V) VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Low Level Output Voltage 4.5 5.5 4.5 5.5 II ICCT ICC IOLD IOHD Input Leakage Current Max ICC /Input Quiescent Supply Current Dynamic Output Current (note 1, 2) 5.5 5.5 5.5 5.5 V I (*) = V IH or V IL VO = 0.1 V or VCC - 0.1 V VO = 0.1 V or VCC - 0.1 V VI = V IH or V IL (*) Test Con dition s Min. 2.0 2.0 Typ. 1.5 1.5 1.5 1.5 4.4 5.4 3.86 4.86 0.001 0.001 4.49 5.49 Value T A = 25 oC Max. -40 to 85 o C Min . 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.36 0.36 0.1 0.6 4 0.1 0.1 0.44 0.44 1 1.5 40 75 -75 0.8 0.8 Max. Unit V V V IO=-50 A IO=-50 A IO=-24 mA IO=-24 mA IO=50 A IO=50 mA IO=24 mA IO=24 mA V VI = VCC or GND VI = VCC -2.1 V VI = VCC or GND VOLD = 1.65 V max VOHD = 3.85 V min A mA A mA mA 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 . (*) All outputs loaded. 4/11 74ACT74 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = t f =3 ns) Symbol Parameter V CC (V) tPLH tPHL tPLH tPHL tw ts th trem fMAX Propagation Delay Time CK to Q Propagation Delay Time PR or CLR to Q or Q CK Pulse Width, HIGH or LOW Setup Time Q to CK HIGH or LOW Hold Time Q to CK HIGH or LOW Removal Time PR or CLR to CK Maximim Clock Frequency 5.0 5.0 (*) T est Cond ition Value T A = 25 oC -40 to 85 o C Min. Typ. Max. Min . Max. 5.0 5.0 1.5 0.5 -0.5 -0.7 100 250 10.0 10.0 5.0 3.0 1.0 1.0 85 11.0 11.0 6.0 3.5 1.0 1.0 Unit ns ns ns ns ns ns MHz (*) 5.0(*) 5.0(*) 5.0(*) 5.0 5.0 (*) (*) (*) Voltage range is 5V 0.5V CAPACITIVE CHARACTERISTICS Symbol Parameter V CC (V) CIN C PD Input Capacitance Power Dissipation Capacitance (note 1) 5.0 5.0 Test Con dition s Min. Typ. 4 43 Value T A = 25 oC Max. -40 to 85 o C Min . Max. pF pF Unit 1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD * VCC * fIN + ICC/n (per circuit) 5/11 74ACT74 TEST CIRCUIT CL = 50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 500 or equivalent RT =ZOUT of pulse generator (typically 50) WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/11 74ACT74 WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 7/11 74ACT74 WAVEFORM 3: RECOVERY TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: PULSE WIDTH 8/11 74ACT74 Plastic DIP14 MECHANICAL DATA mm MIN. a1 B b b1 D E e e3 F I L Z 1.27 3.3 2.54 0.050 8.5 2.54 15.24 7.1 5.1 0.130 0.100 0.51 1.39 0.5 0.25 20 0.335 0.100 0.600 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.055 0.020 0.010 0.787 0.065 inch TYP. MAX. DIM. P001A 9/11 74ACT74 SO14 MECHANICAL DATA DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 8.55 5.8 1.27 7.62 4.0 5.3 1.27 0.68 8 (max.) 0.149 0.181 0.019 8.75 6.2 0.35 0.19 0.5 45 (typ.) 0.336 0.228 0.050 0.300 0.157 0.208 0.050 0.026 0.344 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 P013G 10/11 74ACT74 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersede and replaces all information previously supplied. s SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. (c) 1997 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A . 11/11 |
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